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培訓方式以講課和實驗穿插進行

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課程介紹：

????此課程展現(xiàn)了Incisive設計和驗證平臺的從行為級，RTL級到門級的完整的設計驗證流程，本課程主要是針對具有集成電路設計和驗證基本知識的設計或驗證工程師而準備。通過本課程的培訓使用戶對Cadence的驗證方法和工具使用有一個全面、整體概念，用戶在實際工作中能根據(jù)所掌握的概念和方法，應用先進的驗證方法提高集成電路的驗證效率和質量。

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Incisive??設計驗證平臺介紹：

????要獲得今天的復雜集成電路功能驗證所需的速度和效率要求我們采用一體化的驗證方法。Cadence Incisive平臺適用于從系統(tǒng)設計到系統(tǒng)內設計的所有設計驗證領域 – 嵌入式軟件、控制、數(shù)據(jù)通路、模擬/數(shù)字混合信號。

Incisive平臺是世界上首個單內核驗證平臺，Incisive單內核架構支持Verilog, VHDL, SystemVerilog, SystemC, SCV(SystemC Verification), PSL/Sugar,算法開發(fā)和模擬/數(shù)字混合信號驗證。它采用了通用的用戶界面和調試環(huán)境，支持全事務級的驗證，一體化測試方法，按需加速。Incisive平臺提供業(yè)界快速，高效的驗證方法。

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課程目標：

After completing this course, you should be able to:

■?Briefly describe Incisive simulation

■?Set up your environment for Incisive simulation

■?Compile, elaborate, and simulate your design and testbench

■?Debug your design with the textual and graphical interfaces

■?Incorporate components of “foreign” languages in your simulation

■?Annotate SDF timing data to the HDL portions of your design

■?Incorporate C and C++ applications into your simulation

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課程安排：

Unit 1

Time Topic

09:30-09:45??Introduction & agenda

09:45-10:00??Incisive simulation overview

10:00-10:30??Setting up the simulation environment

10:30-12:00??Compiling your design

12:00-13:30??LUNCH

13:30-02:15??Elaborating your design

02:15-03:45??Simulating your design

03:45-05:00??Debugging with the textual interface

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Unit 2

Time Topic

09:30-10:00??Debugging with the textual interface

10:00-11:15??Debugging with the graphical interface

11:15-12:45??Simulating mixed-language designs

12:45-01:45??LUNCH

01:45-02:00??Introducing simulator utilities

02:00-03:30??[optional] Annotating SDF timing

03:30-05:00??[optional] Linking user applications